1. Technical Field
The present invention relates to a system for booting a computing device; more particularly, a system booted using a NAND flash memory and a booting method thereof.
2. Discussion of Related Art
In every typical personal computer (PC) or computing device such as a personal digital assistant (PDA), a program installed in a basic input/output service (BIOS) is executed when the PC or device is turned on. A number of initialization functions are performed by executing the BIOS program. These functions are typically: checking the CMOS Setup for custom settings; loading the interrupt handlers and device drivers; initializing registers and power management; performing the power-on self-test (POST) for installed components or peripherals such as disk drives; displaying system settings; determining which components are bootable; and initiating the bootstrap sequence. Conventionally, a BIOS (or booting) program is stored in a read only memory (ROM), an erasable programmable read only memory (EPROM) or a NOR-type logic (NOR) flash memory.
If a booting program is stored in a ROM, since ROMs are nonvolatile, the stored program cannot be changed. Any minor changes necessary to the stored program require replacement of the ROM. In the case where a booting program is stored in an EPROM, the previously stored program must be erased if there are changes to the stored program. EPROM erasure further requires a separate component or device. As such, any changes or updates needed in the booting program cannot be easily performed if the program is stored in a ROM or an EPROM. In the case where a booting program is stored in a NOR-logic (NOR) flash memory, the stored program can be erased or updated. However, compared to a NAND-logic (NAND) flash memory, the NOR flash memory are larger in size for a given memory storage capacity and is more expensive to manufacture.
One example of a system with a NAND flash memory storing a BIOS is illustrated in FIG.1, which is disclosed in U.S. Pat. No. 5,535,357. Referring to FIG. 1, a system 10 includes a system bus 17, a combination chip 16 in which a NAND flash memory 18 and an internal interface block 15 are incorporated, and a controller 11 for controlling the combination chip 16 and the system memory 19. The controller 11 can be a central processing unit (CPU), which has a CPU core 12 for performing computing functions, a memory controller 14, and an internal system bus 13 which is internal within the controller 11. The memory controller 14 carries out a memory map between the NAND flash memory 18 and the system memory 19, and uses the internal interface block 15 for interfacing functions performed according to the memory map. The internal interface block 15 temporarily stores data of the NAND flash memory device in a storage device such as a register or RAM, and transfers the temporarily stored data to the system memory through the system bus 17 under control of the memory controller 14.
The internal interface block 15 includes a NAND interface logic 28 for interfacing with the NAND flash memory 18 and a NOR interface logic 29 for interfacing with the system memory 19 or memory controller 14 through system bus 17. The NOR interface logic 29 is circuit conventionally used for interfacing between a NOR flash memory and memory controller and/or system memory. If the flash memory was a NOR flash memory, the NAND interface logic 28 would not be needed to conform signals from the flash memory to ‘NOR interface manner’ (one skilled in the art may refer to this term as “ROM interface manner”), which is data transfer where random access of the memory is possible based on an address of a byte/word unit. In contrast, data transfer by ‘NAND interface manner’ is not by random access, but data of block units is transferred by a block address and a command.
The system 10 transfers data of the NAND flash memory 18 to the internal interface block 15 through the NAND interface logic 28 using the NAND interface manner, and transfers the data to the system memory 19 through the NOR interface logic 29 using the NOR interface manner. Since data access from the NAND flash memory 18 requires traversing the two-stage NAND interface manner and NOR interface manner, data access speed is compromised. Further, system performance rating of such device cannot be optimal because the time required for accessing a booting code stored in the flash memory device by the memory controller is one measure of system performance.
Moreover, since all data of the NAND flash memory 18 need to be loaded into the internal interface block 15 and logic circuit supporting both NAND and NOR interfaces is needed, the internal interface block 15 need to be physically large in size. Accordingly, system 10 as shown in FIG. 1 may suffer from high cost and sub-optimal performance rating.